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misc: chore: Merge into pattern
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@@ -254,8 +254,7 @@ namespace ARMeilleure.Decoders
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}
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// Compare and branch instructions are always conditional.
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if (opCode.Instruction.Name == InstName.Cbz ||
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opCode.Instruction.Name == InstName.Cbnz)
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if (opCode.Instruction.Name is InstName.Cbz or InstName.Cbnz)
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{
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return false;
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}
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@@ -284,7 +283,7 @@ namespace ARMeilleure.Decoders
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// register (Rt == 15 or (mask & (1 << 15)) != 0), and cases where there is
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// a write back to PC (wback == true && Rn == 15), however the later may
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// be "undefined" depending on the CPU, so compilers should not produce that.
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if (opCode is IOpCode32Mem || opCode is IOpCode32MemMult)
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if (opCode is IOpCode32Mem or IOpCode32MemMult)
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{
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int rt, rn;
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@@ -326,15 +325,12 @@ namespace ARMeilleure.Decoders
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}
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// Explicit branch instructions.
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return opCode is IOpCode32BImm ||
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opCode is IOpCode32BReg;
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return opCode is IOpCode32BImm or IOpCode32BReg;
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}
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private static bool IsCall(OpCode opCode)
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{
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return opCode.Instruction.Name == InstName.Bl ||
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opCode.Instruction.Name == InstName.Blr ||
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opCode.Instruction.Name == InstName.Blx;
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return opCode.Instruction.Name is InstName.Bl or InstName.Blr or InstName.Blx;
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}
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private static bool IsException(OpCode opCode)
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@@ -344,9 +340,7 @@ namespace ARMeilleure.Decoders
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private static bool IsTrap(OpCode opCode)
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{
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return opCode.Instruction.Name == InstName.Brk ||
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opCode.Instruction.Name == InstName.Trap ||
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opCode.Instruction.Name == InstName.Und;
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return opCode.Instruction.Name is InstName.Brk or InstName.Trap or InstName.Und;
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}
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public static OpCode DecodeOpCode(IMemoryManager memory, ulong address, ExecutionMode mode)
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