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misc: chore: Merge into pattern

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This commit is contained in:
KeatonTheBot
2025-09-24 13:51:15 -05:00
parent 503dea74c2
commit fa682d406e
157 changed files with 470 additions and 546 deletions
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src/Ryujinx.Cpu/AppleHv/HvExecutionContext.cs
+1 -1
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@@ -219,7 +219,7 @@ namespace Ryujinx.Cpu.AppleHv
address = SynchronousException(memoryManager, ref vcpu);
HvApi.hv_vcpu_set_reg(vcpu.Handle, HvReg.PC, address).ThrowOnError();
}
else if (reason == HvExitReason.Canceled || reason == HvExitReason.VTimerActivated)
else if (reason is HvExitReason.Canceled or HvExitReason.VTimerActivated)
{
if (GetAndClearInterruptRequested())
{
src/Ryujinx.Cpu/LightningJit/Arm32/InstName.cs
+1 -1
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@@ -531,7 +531,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32
{
public static bool IsCall(this InstName name)
{
return name == InstName.BlI || name == InstName.BlxR;
return name is InstName.BlI or InstName.BlxR;
}
public static bool IsSystem(this InstName name)
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/Compiler.cs
+1 -1
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@@ -560,7 +560,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
}
}
Debug.Assert(name == InstName.B || name == InstName.Cbnz, $"Unknown branch instruction \"{name}\".");
Debug.Assert(name is InstName.B or InstName.Cbnz, $"Unknown branch instruction \"{name}\".");
}
private static void RewriteCallInstructionWithTarget(in Context context, uint targetAddress, uint nextAddress, int branchIndex)
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitNeonCommon.cs
+15 -15
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@@ -118,7 +118,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
public static void EmitScalarUnaryF(CodeGenContext context, uint rd, uint rm, uint size, Action<Operand, Operand, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -133,7 +133,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
public static void EmitScalarUnaryF(CodeGenContext context, uint rd, uint rm, uint size, Action<Operand, Operand, uint> action, Action<Operand, Operand> actionHalf)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -161,7 +161,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
uint sf,
Action<Operand, Operand, uint, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -182,7 +182,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
uint sf,
Action<Operand, Operand, uint, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -197,7 +197,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
public static void EmitScalarUnaryFixedF(CodeGenContext context, uint rd, uint rm, uint fbits, uint size, bool is16Bit, Action<Operand, Operand, uint, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -214,7 +214,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
public static void EmitScalarBinaryF(CodeGenContext context, uint rd, uint rn, uint rm, uint size, Action<Operand, Operand, Operand, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -252,7 +252,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
public static void EmitScalarTernaryRdF(CodeGenContext context, uint rd, uint rn, uint rm, uint size, Action<Operand, Operand, Operand, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -276,7 +276,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
uint size,
Action<Operand, Operand, Operand, Operand, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -300,7 +300,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
bool negD,
bool negProduct)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@@ -918,7 +918,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
Action<Operand, Operand, uint, uint> action,
Action<Operand, Operand, uint> actionHalf)
{
Debug.Assert(sz == 0 || sz == 1);
Debug.Assert(sz is 0 or 1);
if (q == 0)
{
@@ -962,7 +962,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
Action<Operand, Operand, uint, uint> action,
Action<Operand, Operand, uint> actionHalf)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
Debug.Assert(size != 3 || q == 1);
if (q == 0)
@@ -1007,7 +1007,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
uint q,
Action<Operand, Operand, uint, uint, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
Debug.Assert(size != 3 || q == 1);
(uint immb, uint immh) = GetImmbImmh(fbits, size);
@@ -1040,7 +1040,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
Action<Operand, Operand, Operand, uint, uint> action,
Action<Operand, Operand, Operand, uint> actionHalf)
{
Debug.Assert(sz == 0 || sz == 1);
Debug.Assert(sz is 0 or 1);
if (q == 0)
{
@@ -1100,7 +1100,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
Action<Operand, Operand, Operand, uint, uint> action,
Action<Operand, Operand, Operand, uint> actionHalf)
{
Debug.Assert(sz == 0 || sz == 1);
Debug.Assert(sz is 0 or 1);
if (q == 0)
{
@@ -1148,7 +1148,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
uint q,
bool negProduct)
{
Debug.Assert(sz == 0 || sz == 1);
Debug.Assert(sz is 0 or 1);
if (q == 0)
{
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitNeonMove.cs
+2 -2
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@@ -252,7 +252,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
}
else
{
Debug.Assert(opc1 == 0 || opc1 == 1);
Debug.Assert(opc1 is 0 or 1);
Debug.Assert(opc2 == 0);
index = opc1 & 1u;
@@ -307,7 +307,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
}
else
{
Debug.Assert(opc1 == 0 || opc1 == 1);
Debug.Assert(opc1 is 0 or 1);
Debug.Assert(opc2 == 0);
Debug.Assert(!u);
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitVfpCompare.cs
+1 -1
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@@ -27,7 +27,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
private static void EmitVcmpVcmpe(CodeGenContext context, uint cond, uint rd, uint rm, uint size, bool zero, bool e)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
uint ftype = size ^ 2u;
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitVfpConvert.cs
+1 -1
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@@ -231,7 +231,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
{
bool unsigned = (op & 1) == 0;
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs
+1 -1
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@@ -1044,7 +1044,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64
{
public static bool IsCall(this InstName name)
{
return name == InstName.Bl || name == InstName.Blr;
return name is InstName.Bl or InstName.Blr;
}
public static bool IsControlFlowOrException(this InstName name)
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Compiler.cs
+2 -2
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@@ -575,7 +575,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
case InstName.Tbz:
uint branchMask;
if (name == InstName.Tbnz || name == InstName.Tbz)
if (name is InstName.Tbnz or InstName.Tbz)
{
originalOffset = ImmUtils.ExtractSImm14Times4(encoding);
branchMask = 0x3fff;
@@ -653,7 +653,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
case InstName.Tbz:
uint branchMask;
if (name == InstName.Tbnz || name == InstName.Tbz)
if (name is InstName.Tbnz or InstName.Tbz)
{
originalOffset = ImmUtils.ExtractSImm14Times4(encoding);
branchMask = 0x3fff;
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Decoder.cs
+2 -2
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@@ -72,7 +72,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
case InstName.Cbz:
case InstName.Tbnz:
case InstName.Tbz:
if (name == InstName.Tbnz || name == InstName.Tbz)
if (name is InstName.Tbnz or InstName.Tbz)
{
originalOffset = ImmUtils.ExtractSImm14Times4(encoding);
}
@@ -369,7 +369,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
case InstName.Cbz:
case InstName.Tbnz:
case InstName.Tbz:
int imm = name == InstName.Tbnz || name == InstName.Tbz
int imm = name is InstName.Tbnz or InstName.Tbz
? ImmUtils.ExtractSImm14Times4(encoding)
: ImmUtils.ExtractSImm19Times4(encoding);
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstEmitSystem.cs
+1 -1
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@@ -230,7 +230,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
case InstName.Bl:
case InstName.Blr:
case InstName.Br:
if (name == InstName.BUncond || name == InstName.Bl)
if (name is InstName.BUncond or InstName.Bl)
{
int imm = ImmUtils.ExtractSImm26Times4(encoding);
src/Ryujinx.Cpu/LightningJit/CodeGen/Arm64/CodeGenCommon.cs
+1 -1
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@@ -28,7 +28,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
// Any value AND all ones will be equal itself, so it's effectively a no-op.
// Any value OR all ones will be equal all ones, so one can just use MOV.
// Any value XOR all ones will be equal its inverse, so one can just use MVN.
if (value == 0 || value == ulong.MaxValue)
if (value is 0 or ulong.MaxValue)
{
immN = 0;
immS = 0;
src/Ryujinx.Cpu/LightningJit/CodeGen/OperandType.cs
+1 -1
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@@ -16,7 +16,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen
{
public static bool IsInteger(this OperandType type)
{
return type == OperandType.I32 || type == OperandType.I64;
return type is OperandType.I32 or OperandType.I64;
}
public static int GetSizeInBytes(this OperandType type)