Commit Graph
10 Commits
Author SHA1 Message Date
LotPandLotP1 521a18f5a7 mono-jit-v2
second attempt at single layer address tables (first attempt https://git.ryujinx.app/projects/Ryubing/pulls/167).
should work with all games now.

Co-authored-by: LotP1 <68976644+LotP1@users.noreply.github.com>
2026-07-17 16:47:59 -05:00
LotPandLotP1 4b255a98db Revert "mono-jit"
This reverts the mono jit PR.
It had several issues that I haven't had time to fix yet.
Expect mono jit v2 in the future with said fixes.

JitCache alignment fixes are still included/fixed.

Co-authored-by: LotP1 <68976644+LotP1@users.noreply.github.com>
2026-07-14 15:43:51 -05:00
LotPandLotP1 6c47892b94 mono-jit
- fix alignment issue with jitcache that could cause a crash.
- Reimplement sparse-jit to only use 1 layer.
    - the old 2 layer approach basically only ever used 1 path due to the bottom-layer size, so doing a double look-up seemed wasteful.
    - changed memory block allocation stategy to allocate based on requested code range instead of the possible address-space.

Co-authored-by: LotP1 <68976644+LotP1@users.noreply.github.com>
2026-07-10 10:03:48 -05:00
KeatonTheBot 76a123b81d misc: chore: Use explicit types & fix object creation 2026-05-30 16:26:50 -05:00
KeatonTheBot 2c50fbcc1f misc: Use nint/nuint instead of IntPtr/UIntPtr 2025-10-29 14:54:07 -05:00
KeatonTheBot fa682d406e misc: chore: Merge into pattern 2025-09-24 13:51:15 -05:00
Marco Carvalho 8547285aba Migrate to .NET 9 2024-12-19 21:18:58 -06:00
LotP1andEvan Husted b8afbc858f JIT Sparse Function Table
More up to date build of the JIT Sparse PR for continued development.
JIT Sparse Function Table was originally developed by riperiperi for the
original Ryujinx project, and decreased the amount of layers in the
Function Table structure, to decrease lookup times at the cost of
slightly higher RAM usage.
This PR rebalances the JIT Sparse Function Table to be a bit more RAM
intensive, but faster in workloads where the JIT Function Table is a
bottleneck. Faster RAM will see a bigger impact and slower RAM (DDR3 and
potentially slow DDR4) will see a slight performance decrease.
This PR also implements a base for a PPTC profile system that could
allow for PPTC with ExeFS mods enabled in the future.
This PR also potentially fixes a strange issue where Avalonia would time
out in some rare instances, e.g. when running ExeFS mods with TotK and a
strange controller configuration.

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Co-authored-by: Evan Husted <gr33m11@gmail.com>
2024-11-26 22:34:00 -06:00
gdkchanandriperiperi 50458b2472 LightningJit: Disable some cache ops and CTR_EL0 access on Windows Arm (#6326)
* LightningJit: Disable some cache ops and CTR_EL0 access on Windows Arm

* Format whitespace

* Delete unused code

* Fix typo

Co-authored-by: riperiperi <rhy3756547@hotmail.com>

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Co-authored-by: riperiperi <rhy3756547@hotmail.com>
2024-03-07 20:55:54 -03:00
gdkchan 427b7d06b5 Implement a new JIT for Arm devices (#6057)
* Implement a new JIT for Arm devices

* Auto-format

* Make a lot of Assembler members read-only

* More read-only

* Fix more warnings

* ObjectDisposedException.ThrowIf

* New JIT cache for platforms that enforce W^X, currently unused

* Remove unused using

* Fix assert

* Pass memory manager type around

* Safe memory manager mode support + other improvements

* Actual safe memory manager mode masking support

* PR feedback
2024-01-20 11:11:28 -03:00